This invention relates to a semiconductor circuit suitable for a normally-on semiconductor switching element turned on even in the case where the gate voltage is zero volt and a normally-off semiconductor switch having a low threshold voltage.
Although a wide band gap semiconductor element of such a material as SiC (carbon silicate), GaN (gallium nitride) or diamond has superior characteristics as a switching element, a typical semiconductor element using this wide band gap semiconductor element such as a junction type FET (hereinafter referred to as JFET), a static induction type transistor (hereinafter referred to as SIT), a metal-semiconductor-field-effect-transistor (hereinafter referred to as MESFET), a heterojunction field effect transistor (hereinafter referred to as HFET), a high electron mobility transistor (hereinafter referred to as HEMT) or an accumulation type FET has a normally-on characteristic with the drain current flowing even when the gate voltage is zero or a normally-off characteristic with a low threshold voltage of not more than 2 to 3 V. A negative power supply circuit for applying a negative voltage between gate and source is required, therefore, to positively turn off the power semiconductor element.
US Patent Application Publication US2003/0179035A1 (FIGS. 3 to 6, and Paragraphs (0025) to (0031)) discloses a method of driving the normally-on JFET, or in particular a controlling circuit in which the gate current can be suppressed at a low level for a JFET having a different breakdown voltage of the diode between gate and source. Also, JP-A-2004-304527 (FIG. 1, and Paragraphs (0015) and (0016)) discloses the conventional bootstrap circuit in which a power supply capacitor of an upper-arm switching element is charged through a lower-arm switching element. Further, JP-A-2004-304527 discloses a method of charging the power supply capacitor of each upper-arm switching element from an auxiliary capacitor used with three sets of charge-discharge switching elements. JP-A-7-23570 (FIGS. 1, 2, and Paragraph (0006)), on the other hand, discloses a SIT activation circuit with a suppressed inrush current in which the gate voltage and the source voltage are applied at different timings for stable activation of the SIT providing a normally-on transistor.
Also, JP-A-2004-242475 (Paragraphs (0034) to (0044)) discloses a circuit having a normally-on FET in which the negative side of a first DC power supply constituting a main power supply is connected with a second DC power supply with the voltage established at the same time as the first DC power supply, and the arm shorting is avoided utilizing the second DC power supply.
The prior art described in US Patent Application Publication US2003/0179035A1 fails to take into consideration a configuration in which a capacitor is used as a power supply for the negative gate voltage of the controlling circuit and charged by the source current of a power semiconductor element.
The prior art described in JP-A-2004-304527, on the other hand, lacks the study of a method to charge the power supply capacitor of the upper-arm switching element through the upper-arm switching element. Further, JP-A-2004-304527, in spite of the study being made about charging the power supply capacitor of the upper-arm switching element from an auxiliary capacitor using three sets of charge-discharge switching elements and auxiliary capacitors, fails to study the method of reducing the number of the charge-discharge capacitors. Also, the use of the power supply capacitor arranged on the lower-arm semiconductor element as a power supply is not studied.
The prior art of JP-A-7-23570 discloses a SIT activation circuit in which the gate voltage and the source voltage are applied at different timings to stably activate the SIT providing a normally-on transistor. Nevertheless, the study is not made about turning off the switching element in collaboration between the switch circuit and a protective circuit and the manner in which the switching element is turned off.
The conventional circuit described in JP-A-2004-242475, in spite of the disclosure of the method of shorting the arm using a second DC power supply, fails to study a case in which the second DC power supply ceases to work.